Generally, semiconductor chips such as of IC and LSI are so tiny, each measuring several millimeters square and about 100 microns thick, that they cannot be easily mounted on printed wiring boards. For the facility of mounting, therefore, such chip usually is placed in a certain container known as an IC or LSI package.
The IC or LSI package has a basic form consisted of a chip mounted on a heat sink which is a heatdissipating metallic base, and bonding wires by which electrode terminals of the chip are bonded to leads for connection to external circuits.
The leads, also called pins, project in a centipede-like fashion out of the package.
Predominant among the types of such IC and LSI packages available today are two; the dual-in-line package (DIP) so called because pins in tow rows extend vertically downward from both edges of the container, and the flat package (FP) with pins projecting from the package body in all four directions in the same plane.
The FP type, which can use comparatively more number of leads (pins) than the DIP type, offers the advantage of achieving a somewhat higher packaging density.
The recent tendency toward even higher integration of LSI has involved a proportional, rapid increase in the number of pins used. Neither the FP nor DIP type can catch up with this tendency, and a novel packaging method has been looked for which could cope with the increasing number of pins per package.
It was with this background that a packaging method called the film carrier (or tape carrier) type has been developed.
The film carrier, as illustrated in FIG. 1, comprises a continuous length of tape 2 having two rows of perforations or sprocket holes 1 formed along the both edges. The tape 2 consists of a substrate of a polyimide, polyester, polyether sulfone (PES), polyparabanic acid (PPA) or other resin and a copper foil bonded onto the substrate. Copper inner leads (fingers for chip bonding) 3 and outer leads (fingers for external connections) 4 are formed on the tape by photoetching. Test pads 5 also are formed.
Microscopic patterns including the inner leads 3 and the outer leads 4 are herein collectively called "lead portion."
The manufacture of such a film carrier will now be described in somewhat more detail in conformity with the commonly employed process. A continuous length of polyimide or other resin tape is punched to provide holes for mounting devices, and a copper foil about 35 microns thick as a metal on which circuits are formed is laminated to the tape base. The copper foil is then coated with a resist and is printed with patterns, followed by exposure to light, development, etching, removal of the resist, and finally plating. This sequence of steps produces fine patterns including the lead portions of FIG. 1.
As FIG. 1 shows, leads formed from the copper foil are closely arranged in a high density so as to project partially into each device hole formed by punching a central portion of the base film to mount a semiconductor chip or the like. The individual leads sometimes have a width as narrow as several ten microns.
A semiconductor chip usually are formed with bumps (electrodes) for connection with the inner leads on the film carrier. The bumps of the semiconductor chip and the inner leads on the film carrier are connected by gang bonding method which is a technique for simultaneously interconnecting all of terminals. When the lead portions are to be mounted on a printed wiring board, the copper foil outer leads together with the semiconductor chip are cut off from the film carrier and then packaged on the board (by stamping).
The tape carrier thus fabricated offers many advantages including the following:
(1) Being conveniently handled as a continuous length of tape, it can be accurately positioned with the aid of the sprocket holes. PA1 (2) The inner leads are seldom broken at the time of bonding as compared with those formed by wire bonding. This permits the adoption of a much finer terminal pitch (as small as about 50 microns). PA1 (3) The gang bonding method renders it possible to carry out the bonding in a single step regardless of the number of terminals to be bonded. PA1 (4) Performance tests of the chips are possible as mounted onto the carrier. PA1 (5) A thin, flexible package can be made because the carrier is thin and pliable. PA1 (6) The packaged chip is easy to replace. PA1 (1) Heat treatment after tin plating. PA1 (2) Coating with an codeposited alloy of tin with nickel, copper, bismuth, antimony, or other metal. PA1 (3) Addition of a sulfur-containing complexing agent or a certain chelate salt to the plating bath. PA1 (4) Adding a palladium or silver salt or the like to the bath so as to distribute the metal throughout the plated film. PA1 (5) Silver-antimony alloy coating of a tinned surface. PA1 (6) Reduction of hydrogen occlusion in the plated metal to a minimum by inversion of the electrode polarity or by the use of ultrasonic energy during plating. PA1 (1) a film carrier for mounting electronic components such as semiconductor chips thereon, characterized in that lead portions formed on the carrier have a plated portion consisting of a tin or tin alloy layer and an indium layer formed thereon, and PA1 (2) a film carrier for mounting electronic components such as semiconductor chips thereon, characterized in that lead portions formed on the carrier have a tin or tin alloy plated portion having an indium diffusion layer. PA1 (3) a method of manufacturing a film carrier for mounting electronic components such as semiconductor chips thereon, characterized by the steps of plating the lead portions formed on the carrier with tin or a tin alloy and then further plating the tin or tin alloy plated surface with indium, and PA1 (4) a method of manufacturing a film carrier for mounting electronic components such as semiconductor chips thereon, characterized by the steps of plating the lead portions formed on the carrier with tin or a tin alloy, further plating the tin or tin alloy plated surface with indium, and then heating the lead portions so as to form a tin or tin alloy plated portion having an indium diffusion layer.
With these and other advantages the film carrier is particularly suited for high-density packaged LSI applications that require more pins than heretofore.
The fine patterns of lead portions formed by etching the copper foil laminated to a film base in the manner described above are usually plated with tin or a tin alloy. The tin or tin alloy plating has several purposes of facilitating the bonding to semiconductor chips (bumps), enhancing the bond strength, and improving the solderability of the outer leads.
However, tin or tin alloy plating presents a serious problem in that it readily causes whiskers to grow out of the surface.
Various proposals have so far been made to prevent the whisker generation. Typical of them are:
None of them have, however, proved satisfactory for the prevention of whisker generation on the tin or tin alloy plating of film carriers. The treatment (1) takes long time and has limitations to the treating temperature because, under certain heating conditions, can cause melting or deformation of plastics. The method (2) is questionable in effects and is likely to affect adversely the corrosion resistance and solderability of the plating, with deterioration of electrical properties and other shortcomings. With (3) and (4) adequate effects are not insured. The method (5) is costly and (6) is limited in application and is unable to avoid the generation of whiskers that result from sources other than occluded hydrogen.
The fine-line circuit patterns on a film carrier include extremely densely arranged leads, which form closely spaced, fine projections unsupported by the resin substrate along the center device hole. The generation of whiskers poses a serious problem since it greatly increases the danger of shorting out not merely the circuits but also wiring on the resin. In electronic devices, the tendency is further toward greater density and higher reliability than ever, and this tendency makes it more and more important to solve the problem of whisker generation.